A conventional differential decoder circuit comprises a pair of differential PNP transistors which are supplied with an operating current by a constant-current source and have emitters commonly connected, wherein an input signal to be decoded is applied to the base input of one of the transistors and a voltage of a constant-voltage source is applied to the base input of the other of the transistors. The transistors compose the first-stage differential circuit. Further, each of collectors of the transistors is connected with the second-stage differential circuit. The differential circuit connected to one of the collectors is composed of PNP transistors, in which the other input signal to be decoded is applied to the base input of a transistor and a voltage of a constant-voltage source is applied to the base of the other transistor. Also, the differential circuit connected to the other collector of the transistors is composed of PNP transistors, in which the voltage of the constant-voltage source is applied to the base of a transistor and the other input signal is applied to the base of the other transistor.
From the collector resistances of the second-stage transistors, the respective decoded output signals to the 2-bit input signals are taken out.
However, when the logical amplitude signals with high-level Vcc and low-level 0V are input, it does not operate stably. Therefore, it needs, for example, means for converting the CMOS(complementary MOS) logic level into the ECL(emitter-coupled logic) level.
This example is composed of two-stage differential circuits. In the case of multi-bit inputs, where the multistage composition is needed, it is difficult for the number of stages of differential connection to be increased since the power source is limited. Also, it cannot provide a high potential output.